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ARCH:010117beq x5,x6,-16 encodes 0xFE6288E3; the B-type immediate is 0x1FF0 = -16 and the target from PC 0x1000 is 0x0FF0, not 0x0FF4

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CA Riscv Btype Immediate ReconstructCA Riscv Beq PC Relative Target

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Instruction-set architecture and assembly semanticsComputer Architecture · Mixed review

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ARCH:010118sum_to(3) pushes four 16-byte frames 0x80000FF0,FE0,FD0,FC0, returns 0,1,3,6, and restores the original sp

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CA Rv32 Abi Frame SaveCA Rv32 Recursion Return Trace

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Instruction-set architecture and assembly semanticsComputer Architecture · Mixed review

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ARCH:010219Unsigned shift-add of 1311 holds P+MQ=143 for eight iterations; Q=0 is not an early stop

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CA Shift Add Product InvariantCA Shift Add Fixed Width Trace

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Datapath and control implementationComputer Architecture · Mixed review

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ARCH:010220A 250ps multicycle clock does not beat a 750ps single-cycle clock on this mix: 75ns versus 101.25ns for 100 instructions

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CA Single Cycle Critical PathCA Multicycle Cpi Mix

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Datapath and control implementationComputer Architecture · Mixed review

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ARCH:010321From SN, TTTNTTTN misses four times and ends in WT; the second pass misses only on the taken-to-not exits

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CA Two Bit Saturating UpdateCA Two Bit Warmup Versus Exit

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Pipelining, hazards, and speculationComputer Architecture · Mixed review

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ARCH:010322T1 wakes the older add; it cannot restore the younger F2 map

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Tomasulo Rat Tag WakeupRob IN Order Commit Values

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Pipelining, hazards, and speculationComputer Architecture · Mixed review

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ARCH:010423Two dirty evictions and three fills: eighty bytes, no trailing flush

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Direct Mapped Index Tag SplitWrite Back Allocate Dirty Traffic

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Caches, virtual memory, and memory hierarchyComputer Architecture · Mixed review

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ARCH:010424A TLB miss walks; a page fault does not install

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Vpn Ppn Offset ConcatTlb Miss Versus Page Fault

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Caches, virtual memory, and memory hierarchyComputer Architecture · Mixed review

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ARCH:010425FR-FCFS serves the open row first; aging must still free the closed one

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Fcfs Versus FR Fcfs CompletionRow Hit Priority Starvation Aging

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Caches, virtual memory, and memory hierarchyComputer Architecture · Mixed review

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ARCH:010526Polling, interrupt, and DMA change winners with B; the unit is CPU cycles

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IO Cpu Occupancy CrossoverPolling Interrupt Dma Regime

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I/O, interrupts, and concurrencyComputer Architecture · Mixed review

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ARCH:010527A capacity-4 descriptor ring posts through wrap and publishes only after data

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Descriptor Ring Monotonic OccupancyIO Release Acquire Publication

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I/O, interrupts, and concurrencyComputer Architecture · Mixed review

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ARCH:010528A nonpreemptive round-robin bus grants M0 then M1 then M2 and needs bounded bursts

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Nonpreemptive Round Robin Grant TraceBounded Burst Wait Argument

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I/O, interrupts, and concurrencyComputer Architecture · Mixed review

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ARCH:010629Roofline time is the max of a compute ceiling and a bandwidth ceiling

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Roofline Ridge And IntensityMin Performance Max Time Bound

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Parallel architecture and performance limitsComputer Architecture · Mixed review

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ARCH:010630False sharing ping-pongs one MESI line without being a data race

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Mesi Upgrade Versus ReadxFalse Sharing Versus Race

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Parallel architecture and performance limitsComputer Architecture · Mixed review

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ARCH:010631A 1024-value binary reduction is span 10 but 36 cycles and memory bound

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Reduction Work Span Level ScheduleTraffic Versus Compute Bound

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Parallel architecture and performance limitsComputer Architecture · Mixed review

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923011A CISC ISA encodes a one-byte opcode followed by a one-byte postbyte that specifies the source operand.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923012Let an n-bit two's-complement displacement d be used by a PC-relative jump whose architectural effect is ``` PC ← a…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923013A 16-bit ISA encodes load and store as: - bits `[15:13]` opcode; `010 = LDR`, `011 = STR` - bits `[12:10]` `Rd` (LD…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923014Consider a stack whose stack pointer `SP` is a 32-bit register.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923015A compare-and-branch instruction ``` BLTZ Rs, offset ``` occupies 4 bytes at address P and has the architectural me…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923016The following six assembly instructions are given.

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ARCH:9923017A machine uses 8-bit opcodes.

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923018An ISA designer claims that a 32-bit fixed-length instruction can provide: - 200 distinct three-register ALU operat…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923019The subroutine-call instruction ``` JAL rd, offset ``` is 32 bits, located at address P, and has architectural mean…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923020A 16-bit processor fetches 16-bit instruction words from even addresses.

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923021The machine-code sequence below is for a 16-bit ISA whose instructions are all one 16-bit word.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923022A scaled-index load is defined by ``` LEA Rd, (Rb, Ri, s) Rd ← Rb + Ri × s ``` where s \in \{1,2,4,8\} is encoded i…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923023Memory is byte-addressable and big-endian.

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923024A processor has a 24-bit address space and 16-bit instructions aligned to even addresses.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923025The following fragment runs on a machine with 32-bit registers, `r0` hardwired to 0, and the ISA - `ADDI rd, rs, im…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923026An instruction decoder consumes a 32-bit word W and classifies it by the 7-bit opcode field W[6:0] and, when requir…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923027A load-linked / store-conditional pair is defined as follows on a uniprocessor with 32-bit registers and 32-bit words.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923028In a 16-bit ISA, the branch instruction ``` BRcc disp8 ``` occupies 2 bytes at even address P.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923029A three-operand instruction `ADD Rd, Rn, shifter_operand` writes `Rd ← Rn + shifter_operand`.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923030The following assembly fragment is the body of a leaf function on a machine with 32-bit registers, a stack that gro…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923031Let an integer be stored in an n-bit two's-complement representation, with the usual weighting -2^{n-1} on the most…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923032Encode each of the decimal integers -73, -1, 0, 1, and 119 as an 8-bit two's-complement bit string, writing bits wi…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923033Compute the 8-bit two's-complement sum of the operands A=01101101 and B=01010011 (spaces are for readability; the m…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923034Let A and B be n-bit two's-complement integers, and let S be the n-bit result of adding A and B in an n-bit adder t…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923035The 6-bit two's-complement encoding of an integer x is 101011 (most significant bit on the left).

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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Problem library

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Search by course or topic.

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Topic choices for Computer Architecture are shortened. Search still covers every problem.

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IndependentSolved with helpIncorrect / unresolvedDraft in progressNot attemptedReview due

Problem results

ProblemsBuild a practice set

ARCH:010117beq x5,x6,-16 encodes 0xFE6288E3; the B-type immediate is 0x1FF0 = -16 and the target from PC 0x1000 is 0x0FF0, not 0x0FF4

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CA Riscv Btype Immediate ReconstructCA Riscv Beq PC Relative Target

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Instruction-set architecture and assembly semanticsComputer Architecture · Mixed review

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ARCH:010118sum_to(3) pushes four 16-byte frames 0x80000FF0,FE0,FD0,FC0, returns 0,1,3,6, and restores the original sp

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CA Rv32 Abi Frame SaveCA Rv32 Recursion Return Trace

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Instruction-set architecture and assembly semanticsComputer Architecture · Mixed review

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ARCH:010219Unsigned shift-add of 1311 holds P+MQ=143 for eight iterations; Q=0 is not an early stop

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CA Shift Add Product InvariantCA Shift Add Fixed Width Trace

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Datapath and control implementationComputer Architecture · Mixed review

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ARCH:010220A 250ps multicycle clock does not beat a 750ps single-cycle clock on this mix: 75ns versus 101.25ns for 100 instructions

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CA Single Cycle Critical PathCA Multicycle Cpi Mix

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Datapath and control implementationComputer Architecture · Mixed review

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ARCH:010321From SN, TTTNTTTN misses four times and ends in WT; the second pass misses only on the taken-to-not exits

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CA Two Bit Saturating UpdateCA Two Bit Warmup Versus Exit

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Pipelining, hazards, and speculationComputer Architecture · Mixed review

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ARCH:010322T1 wakes the older add; it cannot restore the younger F2 map

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Tomasulo Rat Tag WakeupRob IN Order Commit Values

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Pipelining, hazards, and speculationComputer Architecture · Mixed review

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ARCH:010423Two dirty evictions and three fills: eighty bytes, no trailing flush

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Direct Mapped Index Tag SplitWrite Back Allocate Dirty Traffic

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Caches, virtual memory, and memory hierarchyComputer Architecture · Mixed review

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ARCH:010424A TLB miss walks; a page fault does not install

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Vpn Ppn Offset ConcatTlb Miss Versus Page Fault

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Caches, virtual memory, and memory hierarchyComputer Architecture · Mixed review

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ARCH:010425FR-FCFS serves the open row first; aging must still free the closed one

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Fcfs Versus FR Fcfs CompletionRow Hit Priority Starvation Aging

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Caches, virtual memory, and memory hierarchyComputer Architecture · Mixed review

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ARCH:010526Polling, interrupt, and DMA change winners with B; the unit is CPU cycles

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IO Cpu Occupancy CrossoverPolling Interrupt Dma Regime

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I/O, interrupts, and concurrencyComputer Architecture · Mixed review

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ARCH:010527A capacity-4 descriptor ring posts through wrap and publishes only after data

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Descriptor Ring Monotonic OccupancyIO Release Acquire Publication

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I/O, interrupts, and concurrencyComputer Architecture · Mixed review

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ARCH:010528A nonpreemptive round-robin bus grants M0 then M1 then M2 and needs bounded bursts

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Nonpreemptive Round Robin Grant TraceBounded Burst Wait Argument

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I/O, interrupts, and concurrencyComputer Architecture · Mixed review

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ARCH:010629Roofline time is the max of a compute ceiling and a bandwidth ceiling

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Roofline Ridge And IntensityMin Performance Max Time Bound

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Parallel architecture and performance limitsComputer Architecture · Mixed review

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ARCH:010630False sharing ping-pongs one MESI line without being a data race

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Mesi Upgrade Versus ReadxFalse Sharing Versus Race

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Parallel architecture and performance limitsComputer Architecture · Mixed review

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ARCH:010631A 1024-value binary reduction is span 10 but 36 cycles and memory bound

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Reduction Work Span Level ScheduleTraffic Versus Compute Bound

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Parallel architecture and performance limitsComputer Architecture · Mixed review

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923011A CISC ISA encodes a one-byte opcode followed by a one-byte postbyte that specifies the source operand.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923012Let an n-bit two's-complement displacement d be used by a PC-relative jump whose architectural effect is ``` PC ← a…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923013A 16-bit ISA encodes load and store as: - bits `[15:13]` opcode; `010 = LDR`, `011 = STR` - bits `[12:10]` `Rd` (LD…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923014Consider a stack whose stack pointer `SP` is a 32-bit register.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923015A compare-and-branch instruction ``` BLTZ Rs, offset ``` occupies 4 bytes at address P and has the architectural me…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923016The following six assembly instructions are given.

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923017A machine uses 8-bit opcodes.

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923018An ISA designer claims that a 32-bit fixed-length instruction can provide: - 200 distinct three-register ALU operat…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923019The subroutine-call instruction ``` JAL rd, offset ``` is 32 bits, located at address P, and has architectural mean…

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923020A 16-bit processor fetches 16-bit instruction words from even addresses.

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923021The machine-code sequence below is for a 16-bit ISA whose instructions are all one 16-bit word.

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923022A scaled-index load is defined by ``` LEA Rd, (Rb, Ri, s) Rd ← Rb + Ri × s ``` where s \in \{1,2,4,8\} is encoded i…

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923023Memory is byte-addressable and big-endian.

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ARCH:9923024A processor has a 24-bit address space and 16-bit instructions aligned to even addresses.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923025The following fragment runs on a machine with 32-bit registers, `r0` hardwired to 0, and the ISA - `ADDI rd, rs, im…

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923026An instruction decoder consumes a 32-bit word W and classifies it by the 7-bit opcode field W[6:0] and, when requir…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923027A load-linked / store-conditional pair is defined as follows on a uniprocessor with 32-bit registers and 32-bit words.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923028In a 16-bit ISA, the branch instruction ``` BRcc disp8 ``` occupies 2 bytes at even address P.

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923029A three-operand instruction `ADD Rd, Rn, shifter_operand` writes `Rd ← Rn + shifter_operand`.

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923030The following assembly fragment is the body of a leaf function on a machine with 32-bit registers, a stack that gro…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923031Let an integer be stored in an n-bit two's-complement representation, with the usual weighting -2^{n-1} on the most…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923032Encode each of the decimal integers -73, -1, 0, 1, and 119 as an 8-bit two's-complement bit string, writing bits wi…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923033Compute the 8-bit two's-complement sum of the operands A=01101101 and B=01010011 (spaces are for readability; the m…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923034Let A and B be n-bit two's-complement integers, and let S be the n-bit result of adding A and B in an n-bit adder t…

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923035The 6-bit two's-complement encoding of an integer x is 101011 (most significant bit on the left).

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IsaComputer Architecture Problem Solving

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Instruction-set architecture and assembly semanticsComputer Architecture · Calculation

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ARCH:9923001A 16-bit instruction format is partitioned as follows, with bit 15 the most-significant bit: - bits `[15:12]` opcod…

ARCH:9923002A processor uses 32-bit little-endian memory and 32-bit instructions that are always aligned to a multiple of 4.

ARCH:9923003Consider the following addressing-mode definitions for a 16-bit data path.

ARCH:9923004A load-store ISA has 32-bit registers `x0`–`x31`, with `x0` hardwired to 0.

ARCH:9923005An ISA uses an expand-opcode scheme on 16-bit instructions.

ARCH:9923006A 32-bit PC-relative branch is encoded as: - bits `[31:25]` `imm[12|10:5]` - bits `[24:20]` `rs2` - bits `[19:15]`…

ARCH:9923007The following assembly fragment is executed on a machine with 32-bit registers `r0`–`r15`, `r0` hardwired to 0, and…

ARCH:9923008A 12-bit instruction word has the format ``` bits [11:9] opcode bits [8:6] rA bits [5:3] rB bits [2:0] rC ``` for e…

ARCH:9923009A machine has eight 16-bit registers `R0`–`R7` and a 16-bit program counter.

ARCH:9923010The 32-bit instruction format for ALU-register operations is - bits `[31:25]` `funct7` - bits `[24:20]` `rs2` - bit…

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ARCH:9923001A 16-bit instruction format is partitioned as follows, with bit 15 the most-significant bit: - bits `[15:12]` opcod…

ARCH:9923002A processor uses 32-bit little-endian memory and 32-bit instructions that are always aligned to a multiple of 4.

ARCH:9923003Consider the following addressing-mode definitions for a 16-bit data path.

ARCH:9923004A load-store ISA has 32-bit registers `x0`–`x31`, with `x0` hardwired to 0.

ARCH:9923005An ISA uses an expand-opcode scheme on 16-bit instructions.

ARCH:9923006A 32-bit PC-relative branch is encoded as: - bits `[31:25]` `imm[12|10:5]` - bits `[24:20]` `rs2` - bits `[19:15]`…

ARCH:9923007The following assembly fragment is executed on a machine with 32-bit registers `r0`–`r15`, `r0` hardwired to 0, and…

ARCH:9923008A 12-bit instruction word has the format ``` bits [11:9] opcode bits [8:6] rA bits [5:3] rB bits [2:0] rC ``` for e…

ARCH:9923009A machine has eight 16-bit registers `R0`–`R7` and a 16-bit program counter.

ARCH:9923010The 32-bit instruction format for ALU-register operations is - bits `[31:25]` `funct7` - bits `[24:20]` `rs2` - bit…