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Topic choices for Digital Logic are shortened. Search still covers every problem.

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ProblemCourse & topicStatus

DLOG:9918151Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918152Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918153Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918154A 4-bit synchronous binary up-counter with synchronous parallel load uses rising-edge-triggered D flip-flops…

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918155A 4-bit asynchronous (ripple) binary up-counter uses four negative-edge-triggered JK flip-flops, each with J=K=1.

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918156A 4-bit asynchronous binary down-counter uses four negative-edge-triggered JK flip-flops, each with J=K=1.

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918157A 4-bit asynchronous ripple up-counter uses four negative-edge-triggered JK flip-flops, each with J=K=1.

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918158Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

—

DLOG:9918159Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

—

DLOG:9918160Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918161Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918162Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918163Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918164Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918165Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918166Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918167Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918168Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918169Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918170Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918171Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918172An 8-bit register R0 must be copied into an 8-bit register R1.

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918173Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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DLOG:9918174Mathematical problem title

FsmDigital Logic Problem Solving

Finite-state-machine designDigital Logic · Calculation

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A 4-bit synchronous binary up-counter is built from four falling-edge-triggered JK flip-flops

Q_3Q_2Q_1Q_0

, with…

A synchronous BCD (modulo-10) up-counter uses four rising-edge-triggered T flip-flops

Q_3Q_2Q_1Q_0

(Q_3

MSB).

A 3-bit synchronous binary up/down counter uses rising-edge-triggered D flip-flops

Q_2Q_1Q_0

(Q_2

MSB).

A modulo-6 synchronous up-counter uses three rising-edge-triggered JK flip-flops

Q_2Q_1Q_0

(Q_2

MSB).

A 4-bit synchronous binary up-counter

Q_3Q_2Q_1Q_0

(Q_3

MSB) has an asynchronous active-low clear…

A modulo-5 synchronous counter uses three rising-edge-triggered D flip-flops

Q_2Q_1Q_0

.

A

16.000\,\mathrm{MHz}

square-wave clock

\mathrm{CLK}

drives a 4-bit synchronous binary up-counter

A_3A_2A_1A_0

…

A watch-crystal oscillator of frequency

32.768\,\mathrm{kHz}

clocks a 15-stage binary ripple divider built from…

A

6.000\,\mathrm{MHz}

master clock

\mathrm{CLK}

drives a cascade of six synchronous BCD (modulo-10) counters…

A 4-bit serial-in serial-out shift register uses rising-edge-triggered D flip-flops

Q_3Q_2Q_1Q_0

.

A 4-bit serial-in parallel-out shift register uses rising-edge-triggered D flip-flops

Q_3Q_2Q_1Q_0

.

An 8-bit parallel-in serial-out shift register uses rising-edge-triggered D flip-flops

Q_7Q_6\ldots

Q_0

(Q_7

MSB).

A 4-bit universal shift register of rising-edge-triggered D flip-flops

Q_3Q_2Q_1Q_0

has mode inputs

S_1S_0

…

A 5-bit ring counter uses rising-edge-triggered D flip-flops

Q_4Q_3Q_2Q_1Q_0

with…

A 5-bit Johnson (switch-tail, twisted-ring) counter uses rising-edge-triggered D flip-flops

Q_4Q_3Q_2Q_1Q_0

with…

A 6-bit Johnson counter uses rising-edge-triggered D flip-flops

Q_5Q_4Q_3Q_2Q_1Q_0

with

D_0=Q_5'

and

D_{i+1}=Q_i

…

Two 4-bit registers

A=A_3A_2A_1A_0

and

B=B_3B_2B_1B_0

share a rising-edge clock.

Two identical 8-bit rising-edge-triggered D registers

R_A

and

R_B

form a single-cycle pipeline.

Adjacent stages of a shift register are rising-edge-triggered D flip-flops with

Q_i

connected to

D_{i+1}

through a…