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Topic choices for Digital Logic are shortened. Search still covers every problem.

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ProblemCourse & topicStatus

DLOG:9918101Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918102Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918103A 4-to-2 priority encoder uses active-low request inputs…

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918104Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918105Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918106A permanently enabled 3-to-8 decoder has address inputs A,B,C with A most significant and active-high outputs…

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918107A tri-state buffer has data input D, active-high enable EN, and output Y.

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918108Four tri-state buffers drive a one-bit bus B.

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918109A 4-bit data word can be routed to a single output by either of two combinational networks.

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918110A BCD-to-decimal decoder has four inputs WXYZ with W most significant, interpreted as an unsigned binary integer…

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918111An 8-to-3 priority encoder is assembled from two 4-to-2 priority encoders and additional gates.

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918112Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918113Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918114Four identical 2-to-1 multiplexers share a common select S.

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918115Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918116Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

—

DLOG:9918117Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

—

DLOG:9918118Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918119Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918120Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918121A cross-coupled NOR SR latch is built from two ideal zero-delay NOR gates.

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918122A cross-coupled NAND SR latch is built from two ideal zero-delay NAND gates.

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918123Mathematical problem title

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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DLOG:9918124A level-sensitive D latch has enable C (active high) and data D.

SequentialDigital Logic Problem Solving

Latches, flip-flops, and sequential circuitsDigital Logic · Calculation

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Showing 24 of 50 matching problems.

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A 4-to-2 priority encoder has request inputs

I_3,I_2,I_1,I_0

, binary outputs

A_1,A_0

, and a valid flag GS.

An 8-to-3 priority encoder has request inputs

I_7,\ldots,I_0

, binary outputs

A_2,A_1,A_0

, and a valid flag V.

A 16-to-1 multiplexer with data lines

X_0,\ldots,X_{15}

and select word

S_3S_2S_1S_0

(S_3

most significant) is…

The Boolean function

F(A,B,C,D)=\sum m(1,3,4,5,9,11,14,15)

uses variable order

A,B,C,D

with

A

most significant.

A 4-to-1 multiplexer has select pair

S_1S_0

(S_1

more significant) and data pins

I_0,I_1,I_2,I_3

.

An 8-bit address

A_7A_6A_5A_4A_3A_2A_1A_0

(A_7

most significant) is decoded by a 3-to-8 decoder whose address pins…

The incompletely specified function

F(A,B,C,D)=\sum m(0,2,5,7,8,10,13)+d(1,6,11,14)

uses variable order

A,B,C,D

…

An 8-to-3 priority encoder has active-high requests

I_7,\ldots,I_0

(I_7

highest priority), active-high enable EN…

Four bus masters

M_3,M_2,M_1,M_0

share a one-bit wired bus B.

A 4-bit combinational rotate-left unit has data input

A=A_3A_2A_1A_0

(A_3

most significant), rotate distance k…

The five-variable function

F(A,B,C,D,E)=\sum m(0,1,3,7,8,11,12,15,16,17,20,23,24,28,30)

uses variable order…

A

2\times

2 combinational switch has data inputs U,V, data outputs P,Q, and control word

C_1C_0

.

A gated NOR SR latch is formed by AND-gating the external inputs with an enable:

S_{\mathrm{int}}=S\cdot

E and…