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Topic choices for Digital Logic are shortened. Search still covers every problem.

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ProblemsClear skill: Timing Hdl Build a practice set

ProblemCourse & topicStatus

DLOG:9918251Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918252Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918253A synchronous block is clocked at period T by a PLL.

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918254A scan-connected register pair in the same clock domain has a combinational path that, in functional mode, is a…

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918255Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918256Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918257Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918258Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918259Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918260A four-phase bundled-data handshake connects a sender in domain S to a receiver in domain R.

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918261Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918262A bank of 16 edge-triggered registers shares an enable E.

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918263An asynchronous modulo-4 incrementer is specified by the flow table on four stable states with a single input X (a…

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918264Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918265A finite-state machine uses a single asynchronous-reset flip-flop bank.

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918266Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918267Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918268A three-stage bundled-data self-timed pipeline uses Muller C-elements to generate local handshake clocks.

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918269A combinational block intended to be acyclic is synthesised to the following netlist, where each named gate has…

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918270A three-stage edge-triggered pipeline in clock domain P at candidate period T receives a 1-bit asynchronous start…

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918271An unsigned integer divider of word width n=8 implements non-restoring division.

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918272Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918273Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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DLOG:9918274Mathematical problem title

Timing HdlDigital Logic Problem Solving

Timing, clocking, and HDL verificationDigital Logic · Mixed review

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Showing 24 of 50 matching problems.

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Two positive-edge-triggered D flip-flops

F_1

(launch) and

F_2

(capture) are connected by a combinational cloud C.

A three-stage pipeline has edge-triggered registers

R_0,R_1,R_2,R_3

and combinational stages

S_1,S_2,S_3

in series:…

In a 500 MHz

(T=2.00\,\mathrm{ns})

synchronous controller, STA reports four paths from register

R_A

to register…

A two-phase latch pipeline alternates transparent-low latches

L_i^\ell

and transparent-high latches

L_i^h

.

An asynchronous input

D_{\mathrm{async}}

of mean event rate

f_{\mathrm{d}}=25\,\mathrm{MHz}

(Poisson edges) is…

A multi-flop synchronizer consists of

n\ge

2 identical back-to-back flip-flops clocked at…

A 4-bit incrementer in clock domain A

(f_A=300\,\mathrm{MHz})

produces a binary count

C\in\{0,1,\ldots,15\}

…

A product ships

N=2.5\times

10^{5}

identical SoCs, each containing M=48 independent two-flop synchronizers.

A one-hot datapath multiplexer with four sources

D_0,D_1,D_2,D_3

is steered by a one-hot select vector

S_3

S_2

S_1

…

A one-hot FSM has five legal states

S_0,\ldots,S_4

, encoded on five flip-flops

Q_0,\ldots,Q_4

with exactly one bit…

A scan chain crosses from clock domain

\mathrm{clk}_1

(f_1=400\,\mathrm{MHz})

to clock domain

\mathrm{clk}_2

…

A coprocessor evaluates the cubic

y = a_3 x^3 + a_2 x^2 + a_1 x + a_0

by Horner’s rule…

A 32-bit adder is implemented as a Kogge–Stone prefix adder with bitwise generate

g_i=a_i

b_i

and propagate…

A

16\times

16 two’s-complement multiplier uses radix-4 Booth recoding and a Wallace carry-save tree, then a 32-bit…