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EMB:010117Ideal 12-bit ADC over [0,3.3V] maps 2.2V to 2730, 1.65V to 2048, 3.3V to 4095; code 2730 occupies [9009/4096, 90123/40960)

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Emb Adc Saturating Floor CodeEmb Adc Half Open Bin Midpoint

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Mixed review

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EMB:010118Little-endian 30 0D encodes signed Q4 -45; A0 02 encodes 42; packed word 0x02A00D30; mean -3/2

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Emb LE Twelve Bit Signed ExtractEmb Q4 Pack And Mean

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Mixed review

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EMB:010219Split-32 increment 0x0001FFFF to 0x00020000 can tear to 0x00010000; seqlock 10 to 11 to 12 yields only old or new

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Emb Torn Split32 WitnessEmb Seqlock Even Equal Accept

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Interrupts, concurrency, and shared stateEmbedded Systems · Mixed review

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EMB:010220L(C6) at t0, M(C4) at t1, H(C2) at t2 run L[0,1], M[1,2], H[2,4], M[4,7], L[7,12]; responses 12, 6, 2; nest 3

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Emb Fixed Priority Preempt TraceEmb Response Time And Nesting

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Interrupts, concurrency, and shared stateEmbedded Systems · Mixed review

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EMB:010221FIFO cap 4, produce at 3k, consume at 5k, producer first on ties; first overflow at t=30 with 10 attempts, 9 successes, 6 consumed, occupancy 3

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Emb Fifo Producer First TraceEmb Rate Implies Eventual Overflow

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Interrupts, concurrency, and shared stateEmbedded Systems · Mixed review

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EMB:01032216-bit counter 65530 plus delay 20 wraps to target 14; elapsed 11,19,20; naive now>=14 fires now

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Emb U16 Wrap Deadline TargetEmb U16 Modular Elapsed Signed Half

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Timers, scheduling, and real-time constraintsEmbedded Systems · Mixed review

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EMB:01032310 MHz into exact-average 3 kHz uses 3333,3333,3334 with phase -1/3,-2/3,0 and 10000 clocks per 3 ticks

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Emb Bresenham Divider PatternEmb Interval Error Phase Close

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Timers, scheduling, and real-time constraintsEmbedded Systems · Mixed review

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EMB:010424UART 8N1 at 115200 carries 11520 B/s; a 68-byte frame is 680 bits in 17/2880 s, 100 pkt/s uses 85/144, max 169

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Emb Uart 8n1 Byte And Packet TimeEmb Uart Utilization And Max Rate

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Serial buses and communication protocolsEmbedded Systems · Mixed review

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EMB:010425Dominant-zero arbitration of 1011000 vs 1010000 differs at bit 4: bus 0, A loses, B wins with 1010000

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Emb Dominant Zero First DifferenceEmb Arbitration Loser Winner

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Serial buses and communication protocolsEmbedded Systems · Mixed review

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EMB:010426Selective-repeat with 3-bit sequence numbers needs W<=4; W=5 makes the next window {5,6,7,0,1} overlap delayed 0,1

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Emb SR Window Half ModulusEmb SR Wrap Overlap Witness

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Serial buses and communication protocolsEmbedded Systems · Mixed review

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EMB:010527A u8,u32,u16 record pads to offsets 0,4,8 and size 12; reordering to u32,u16,u8 yields 0,4,6 and size 8, saving 400 B over 100 records

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Emb C Struct Natural Alignment OffsetsEmb C Struct Reorder Tail Pad Savings

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Memory, energy, and reliability budgetsEmbedded Systems · Mixed review

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EMB:010528Deepest stack is 32+48+16 plus 64 plus 40 = 200 B; from 0x20001000 the SP is 0x20000F38, a 256 B region leaves 56 B, and a 32 B reserve leaves 24 B

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Emb Nested Isr Stack SumEmb Downward SP Watermark Reserve

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Memory, energy, and reliability budgetsEmbedded Systems · Mixed review

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EMB:010529One update a minute on 16 pages of endurance 1000 lasts 1000 min unleveled, 16000 min = 100/9 days leveled, and 14000 min = 175/18 days with two reserved pages

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Emb Flash Single Page Versus LevelingEmb Flash Reserved Page Lifetime Days

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Memory, energy, and reliability budgetsEmbedded Systems · Mixed review

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EMB:010630Guarded two-door opens and closes preserve not(L&&R) by induction on {00,10,01}; non-atomic simultaneous opens from 00 reach 11

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Emb Interlock Reachable Set InductionEmb Simultaneous Unguarded Open Race

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State-machine verification and safety boundariesEmbedded Systems · Mixed review

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EMB:010631Monitor OK-1->SUSPECT-1->SAFE, a match 0 resets SUSPECT, SAFE is absorbing with output 0; input 0,1,0,1,1 yields OK,SUSPECT,OK,SUSPECT,SAFE

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Emb Two Mismatch Monitor TraceEmb Absorbing Safe Isolated Mismatch

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State-machine verification and safety boundariesEmbedded Systems · Mixed review

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925011A 32-bit device-identification register \mathrm{ID} is mapped at byte address \mathtt{0x40023C00} on a little-endia…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925012Two open-drain GPIO pins, \mathrm{PA}2 on MCU A and \mathrm{PB}6 on MCU B, are tied to one net N.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925013Anvil-M3 provides a bit-band alias for the 1 MiB SRAM region [\mathtt{0x20000000},\mathtt{0x200FFFFF}].

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925014USART0 on Anvil-M0 is a 32-bit peripheral at base address B=\mathtt{0x40011000}.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925015GPIOA on Anvil-M3 has 16 pins.

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Mcu IOEmbedded Systems Problem Solving

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EMB:9925016Anvil-M0 implements two additional rules.

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Mcu IOEmbedded Systems Problem Solving

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EMB:9925017A little-endian Anvil-M0 C implementation lays out the following structure in SRAM.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925018GPIOA pin \mathrm{PA}4 on Anvil-M0 is configured as an open-drain output with no internal pull.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925019An 8-bit little-endian microcontroller Nest-8 has a 16-bit free-running timer \mathrm{TCNT} mapped as two bytes: \m…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925020A combinational address decoder on Kite-16 has active-high chip selects defined by The remaining address bits A_{13…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925021Pin \mathrm{PA}2 of Anvil-M0 is 5\,\mathrm{V}-tolerant under a stated subset of modes.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925022GPIOA includes a write-only 32-bit toggle register \mathrm{TGL} at \mathtt{0x40020018}.

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Mcu IOEmbedded Systems Problem Solving

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EMB:9925023A 16-bit external memory is attached to a microcontroller with data bus D_{15}\ldots D_{0} and byte-enable strobes.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925024A little-endian Anvil-M0 holds a 32-bit unsigned integer X=\mathtt{0x0A0B0C0D} in register \mathrm{r0}.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925025On Anvil-M3, GPIOA is clock-gated by bit 0 of the 32-bit register \mathrm{RCC\_AHB1ENR} at address \mathtt{0x400238…

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Mcu IOEmbedded Systems Problem Solving

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EMB:9925026GPIOA reset value of \mathrm{MODER} on this Anvil-M3 part is \mathtt{0xA8000000}.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925027An 8\,\mathrm{KiB} SRAM is mapped at [\mathtt{0x20000000},\mathtt{0x20001FFF}].

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925028Anvil-M0 runs from a processor clock f_{\mathrm{clk}}=12.00\,\mathrm{MHz} with one clock equal to one cycle.

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Mcu IOEmbedded Systems Problem Solving

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EMB:9925029A 16-bit character LCD is attached to Nest-8 through three GPIO ports, all configured as push-pull outputs.

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Mcu IOEmbedded Systems Problem Solving

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EMB:9925030A student submits the following bring-up description for an Anvil-M3 board.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925031A 12-bit successive-approximation ADC converts analog voltages in the unipolar range from V_{\mathrm{REF}-}=0.000\,…

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Mcu IOEmbedded Systems Problem Solving

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EMB:9925032An MCU ADC samples through an internal switch of resistance R_{\mathrm{ADC}}=1.50\,\mathrm{k}\Omega onto a hold cap…

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Mcu IOEmbedded Systems Problem Solving

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EMB:9925033A 12-bit SAR ADC requires 12 conversion clocks after the sampling interval.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925034A 12-bit ADC is configured for true differential conversion.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925035A 12-bit voltage-mode DAC has reference V_{\mathrm{REF}}=3.000\,\mathrm{V} and code-to-voltage map where D\in\{0,1,…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Problem library

Find a problem

Search by course or topic.

Search problems

Area

AllMathPhysics

SubjectCourseTopic

Topic choices for Embedded Systems are shortened. Search still covers every problem.

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StatusSkillProblem styleFind a private labelPrivate labelFavorites

Clear

Browsing still works.Sign in to add progress, saved problems and private labels.

Progress labels

IndependentSolved with helpIncorrect / unresolvedDraft in progressNot attemptedReview due

Problem results

ProblemsBuild a practice set

EMB:010117Ideal 12-bit ADC over [0,3.3V] maps 2.2V to 2730, 1.65V to 2048, 3.3V to 4095; code 2730 occupies [9009/4096, 90123/40960)

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Emb Adc Saturating Floor CodeEmb Adc Half Open Bin Midpoint

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Mixed review

Progress not loaded

EMB:010118Little-endian 30 0D encodes signed Q4 -45; A0 02 encodes 42; packed word 0x02A00D30; mean -3/2

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Emb LE Twelve Bit Signed ExtractEmb Q4 Pack And Mean

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Mixed review

Progress not loaded

EMB:010219Split-32 increment 0x0001FFFF to 0x00020000 can tear to 0x00010000; seqlock 10 to 11 to 12 yields only old or new

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Emb Torn Split32 WitnessEmb Seqlock Even Equal Accept

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Interrupts, concurrency, and shared stateEmbedded Systems · Mixed review

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EMB:010220L(C6) at t0, M(C4) at t1, H(C2) at t2 run L[0,1], M[1,2], H[2,4], M[4,7], L[7,12]; responses 12, 6, 2; nest 3

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Emb Fixed Priority Preempt TraceEmb Response Time And Nesting

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Interrupts, concurrency, and shared stateEmbedded Systems · Mixed review

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EMB:010221FIFO cap 4, produce at 3k, consume at 5k, producer first on ties; first overflow at t=30 with 10 attempts, 9 successes, 6 consumed, occupancy 3

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Emb Fifo Producer First TraceEmb Rate Implies Eventual Overflow

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Interrupts, concurrency, and shared stateEmbedded Systems · Mixed review

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EMB:01032216-bit counter 65530 plus delay 20 wraps to target 14; elapsed 11,19,20; naive now>=14 fires now

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Emb U16 Wrap Deadline TargetEmb U16 Modular Elapsed Signed Half

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Timers, scheduling, and real-time constraintsEmbedded Systems · Mixed review

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EMB:01032310 MHz into exact-average 3 kHz uses 3333,3333,3334 with phase -1/3,-2/3,0 and 10000 clocks per 3 ticks

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Emb Bresenham Divider PatternEmb Interval Error Phase Close

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Timers, scheduling, and real-time constraintsEmbedded Systems · Mixed review

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EMB:010424UART 8N1 at 115200 carries 11520 B/s; a 68-byte frame is 680 bits in 17/2880 s, 100 pkt/s uses 85/144, max 169

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Emb Uart 8n1 Byte And Packet TimeEmb Uart Utilization And Max Rate

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Serial buses and communication protocolsEmbedded Systems · Mixed review

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EMB:010425Dominant-zero arbitration of 1011000 vs 1010000 differs at bit 4: bus 0, A loses, B wins with 1010000

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Emb Dominant Zero First DifferenceEmb Arbitration Loser Winner

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Serial buses and communication protocolsEmbedded Systems · Mixed review

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EMB:010426Selective-repeat with 3-bit sequence numbers needs W<=4; W=5 makes the next window {5,6,7,0,1} overlap delayed 0,1

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Emb SR Window Half ModulusEmb SR Wrap Overlap Witness

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Serial buses and communication protocolsEmbedded Systems · Mixed review

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EMB:010527A u8,u32,u16 record pads to offsets 0,4,8 and size 12; reordering to u32,u16,u8 yields 0,4,6 and size 8, saving 400 B over 100 records

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Emb C Struct Natural Alignment OffsetsEmb C Struct Reorder Tail Pad Savings

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Memory, energy, and reliability budgetsEmbedded Systems · Mixed review

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EMB:010528Deepest stack is 32+48+16 plus 64 plus 40 = 200 B; from 0x20001000 the SP is 0x20000F38, a 256 B region leaves 56 B, and a 32 B reserve leaves 24 B

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Emb Nested Isr Stack SumEmb Downward SP Watermark Reserve

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Memory, energy, and reliability budgetsEmbedded Systems · Mixed review

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EMB:010529One update a minute on 16 pages of endurance 1000 lasts 1000 min unleveled, 16000 min = 100/9 days leveled, and 14000 min = 175/18 days with two reserved pages

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Emb Flash Single Page Versus LevelingEmb Flash Reserved Page Lifetime Days

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Memory, energy, and reliability budgetsEmbedded Systems · Mixed review

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EMB:010630Guarded two-door opens and closes preserve not(L&&R) by induction on {00,10,01}; non-atomic simultaneous opens from 00 reach 11

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Emb Interlock Reachable Set InductionEmb Simultaneous Unguarded Open Race

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State-machine verification and safety boundariesEmbedded Systems · Mixed review

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EMB:010631Monitor OK-1->SUSPECT-1->SAFE, a match 0 resets SUSPECT, SAFE is absorbing with output 0; input 0,1,0,1,1 yields OK,SUSPECT,OK,SUSPECT,SAFE

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Emb Two Mismatch Monitor TraceEmb Absorbing Safe Isolated Mismatch

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State-machine verification and safety boundariesEmbedded Systems · Mixed review

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925011A 32-bit device-identification register \mathrm{ID} is mapped at byte address \mathtt{0x40023C00} on a little-endia…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925012Two open-drain GPIO pins, \mathrm{PA}2 on MCU A and \mathrm{PB}6 on MCU B, are tied to one net N.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925013Anvil-M3 provides a bit-band alias for the 1 MiB SRAM region [\mathtt{0x20000000},\mathtt{0x200FFFFF}].

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925014USART0 on Anvil-M0 is a 32-bit peripheral at base address B=\mathtt{0x40011000}.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925015GPIOA on Anvil-M3 has 16 pins.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925016Anvil-M0 implements two additional rules.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925017A little-endian Anvil-M0 C implementation lays out the following structure in SRAM.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925018GPIOA pin \mathrm{PA}4 on Anvil-M0 is configured as an open-drain output with no internal pull.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925019An 8-bit little-endian microcontroller Nest-8 has a 16-bit free-running timer \mathrm{TCNT} mapped as two bytes: \m…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925020A combinational address decoder on Kite-16 has active-high chip selects defined by The remaining address bits A_{13…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925021Pin \mathrm{PA}2 of Anvil-M0 is 5\,\mathrm{V}-tolerant under a stated subset of modes.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925022GPIOA includes a write-only 32-bit toggle register \mathrm{TGL} at \mathtt{0x40020018}.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925023A 16-bit external memory is attached to a microcontroller with data bus D_{15}\ldots D_{0} and byte-enable strobes.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925024A little-endian Anvil-M0 holds a 32-bit unsigned integer X=\mathtt{0x0A0B0C0D} in register \mathrm{r0}.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925025On Anvil-M3, GPIOA is clock-gated by bit 0 of the 32-bit register \mathrm{RCC\_AHB1ENR} at address \mathtt{0x400238…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925026GPIOA reset value of \mathrm{MODER} on this Anvil-M3 part is \mathtt{0xA8000000}.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925027An 8\,\mathrm{KiB} SRAM is mapped at [\mathtt{0x20000000},\mathtt{0x20001FFF}].

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925028Anvil-M0 runs from a processor clock f_{\mathrm{clk}}=12.00\,\mathrm{MHz} with one clock equal to one cycle.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925029A 16-bit character LCD is attached to Nest-8 through three GPIO ports, all configured as push-pull outputs.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925030A student submits the following bring-up description for an Anvil-M3 board.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925031A 12-bit successive-approximation ADC converts analog voltages in the unipolar range from V_{\mathrm{REF}-}=0.000\,…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925032An MCU ADC samples through an internal switch of resistance R_{\mathrm{ADC}}=1.50\,\mathrm{k}\Omega onto a hold cap…

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925033A 12-bit SAR ADC requires 12 conversion clocks after the sampling interval.

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Mcu IOEmbedded Systems Problem Solving

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925034A 12-bit ADC is configured for true differential conversion.

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Microcontrollers, memory-mapped I/O, and peripheralsEmbedded Systems · Calculation

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EMB:9925035A 12-bit voltage-mode DAC has reference V_{\mathrm{REF}}=3.000\,\mathrm{V} and code-to-voltage map where D\in\{0,1,…

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Problem results

EMB:9925001A 16-bit microcontroller Kite-16 has a single 16-bit address bus and a 16-bit data bus.

EMB:9925002A 32-bit little-endian microcontroller Anvil-M0 fetches two 32-bit words from byte addresses \mathtt{0x00000000} an…

EMB:9925003A Harvard microcontroller HX16 has two independent address spaces.

EMB:9925004A 32-bit little-endian core Anvil-M0 has a byte-addressable data memory.

EMB:9925005An 8-bit GPIO port PORTA on microcontroller Nest-8 has three 8-bit registers.

EMB:9925006A 16-bit GPIO port on Anvil-M0 has an output-data register \mathrm{ODR} and a set/reset register \mathrm{BSRR}.

EMB:9925007Anvil-M0 requires natural alignment: an 8-bit access may use any byte address; a 16-bit access may use only an even…

EMB:9925008Each pin \mathrm{PA}n of GPIOA on Anvil-M0 has a 4-bit alternate-function field \mathrm{AF}n\in\{0,1,\ldots,15\}.

EMB:9925009Anvil-M3 uses a 32-bit unified byte address space.

EMB:9925010GPIOA on Anvil-M0 provides three 32-bit registers that affect the same 16 output latches \mathrm{ODR}[15:0].

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Problem results

EMB:9925001A 16-bit microcontroller Kite-16 has a single 16-bit address bus and a 16-bit data bus.

EMB:9925002A 32-bit little-endian microcontroller Anvil-M0 fetches two 32-bit words from byte addresses \mathtt{0x00000000} an…

EMB:9925003A Harvard microcontroller HX16 has two independent address spaces.

EMB:9925004A 32-bit little-endian core Anvil-M0 has a byte-addressable data memory.

EMB:9925005An 8-bit GPIO port PORTA on microcontroller Nest-8 has three 8-bit registers.

EMB:9925006A 16-bit GPIO port on Anvil-M0 has an output-data register \mathrm{ODR} and a set/reset register \mathrm{BSRR}.

EMB:9925007Anvil-M0 requires natural alignment: an 8-bit access may use any byte address; a 16-bit access may use only an even…

EMB:9925008Each pin \mathrm{PA}n of GPIOA on Anvil-M0 has a 4-bit alternate-function field \mathrm{AF}n\in\{0,1,\ldots,15\}.

EMB:9925009Anvil-M3 uses a 32-bit unified byte address space.

EMB:9925010GPIOA on Anvil-M0 provides three 32-bit registers that affect the same 16 output latches \mathrm{ODR}[15:0].