Practice problems with hints and solutions · ProofAnvil Browsing still works.Sign in to use progress, saved problems and private labels. Problem search and previews remain available. Progress labels
IndependentSolved with helpIncorrect / unresolvedDraft in progressNot attemptedReview due
Problem results
ProblemCourse & topicStatus
ARCH:9923001Mathematical problem title
IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Showing 24 of 50 matching problems.
A 16-bit instruction format is partitioned as follows, with bit 15 the most-significant bit: - bits [15:12]…
A processor uses 32-bit little-endian memory and 32-bit instructions that are always aligned to a multiple of 4.
Consider the following addressing-mode definitions for a 16-bit data path.
A load-store ISA has 32-bit registers x0–x31, with x0 hardwired to 0.
An ISA uses an expand-opcode scheme on 16-bit instructions.
A 32-bit PC-relative branch is encoded as: - bits [31:25] imm[12|10:5] - bits [24:20] rs2 - bits [19:15]…
The following assembly fragment is executed on a machine with 32-bit registers r0–r15, r0 hardwired to 0…
A 12-bit instruction word has the format `` bits [11:9] opcode bits [8:6] rA bits [5:3] rB bits [2:0] rC `` for…
A machine has eight 16-bit registers R0–R7 and a 16-bit program counter.
The 32-bit instruction format for ALU-register operations is - bits [31:25] funct7 - bits [24:20] rs2…
A CISC ISA encodes a one-byte opcode followed by a one-byte postbyte that specifies the source operand.
Let an n-bit two's-complement displacement d be used by a PC-relative jump whose architectural effect is ``` PC ←…
A 16-bit ISA encodes load and store as: - bits [15:13] opcode; 010 = LDR, 011 = STR - bits [12:10] Rd…
Consider a stack whose stack pointer SP is a 32-bit register.
A compare-and-branch instruction `` BLTZ Rs, offset `` occupies 4 bytes at address P and has the architectural…
The following six assembly instructions are given.
A machine uses 8-bit opcodes.
An ISA designer claims that a 32-bit fixed-length instruction can provide: - 200 distinct three-register ALU…
The subroutine-call instruction `` JAL rd, offset `` is 32 bits, located at address P, and has architectural…
A 16-bit processor fetches 16-bit instruction words from even addresses.
The machine-code sequence below is for a 16-bit ISA whose instructions are all one 16-bit word.
A scaled-index load is defined by `` LEA Rd, (Rb, Ri, s) Rd ← Rb + Ri × s `` where s ∈ {1,2,4,8} is encoded… Memory is byte-addressable and big-endian.
A processor has a 24-bit address space and 16-bit instructions aligned to even addresses.