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ProblemCourse & topicStatus

ARCH:9923101A 32-bit multi-cycle RISC processor executes the six-instruction sequence below, starting with…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923102In a multi-cycle RISC processor the register-file write occurs only in a dedicated writeback state that follows…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923103Mathematical problem title

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923104A multi-cycle RISC processor’s data memory is synchronous: a read or write begun on the rising clock edge of a…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923105Mathematical problem title

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923106The instruction j (opcode 000010) is implemented in a 32-bit multi-cycle RISC processor in three cycles…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923107A 32-bit multi-cycle RISC processor is extended with the instruction jal (opcode 000011).

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923108Control signals of a multi-cycle RISC processor are generated by a Moore FSM: each signal’s value in a cycle…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923109Mathematical problem title

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923110Mathematical problem title

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923111Mathematical problem title

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923112A 32-bit multi-cycle RISC processor and an otherwise identical pipelined processor are compared on resource…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923113The equality test for beq on a 32-bit multi-cycle RISC processor is implemented by performing A-B in…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923114A multi-cycle RISC processor’s clock period is set by the maximum of: memory access 220 ps, ALU 180 ps…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923115Prove the following claim.

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923116A 32-bit multi-cycle RISC processor supports an interrupt by transitioning from any state in which MemRead or…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923117The IorD multiplexor of a 32-bit multi-cycle RISC processor selects the memory address: IorD =0 selects PC, IorD…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923118Mathematical problem title

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923119Mathematical problem title

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923120A 32-bit multi-cycle RISC processor is described by the following resource constraints: one ALU, one memory port…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923121Consider a classic 5-stage RISC pipeline with stages IF (instruction fetch), ID (decode and register-file read)…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923122A 32-bit RISC uses the following instruction formats.

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923123A single-cycle 32-bit RISC datapath (no pipeline registers) has the following combinational delays: instruction…

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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ARCH:9923124The same component delays as in Problem 123 are used to build a classic 5-stage pipeline.

PipelineComputer Architecture Problem Solving

Pipelining, hazards, and speculationComputer Architecture · Calculation

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A designer claims that

S_\mathrm{Fetch}

and

S_\mathrm{Decode}

of a 32-bit multi-cycle RISC processor can be merged…

Let M be a 32-bit multi-cycle RISC processor whose only ALU-using states are

S_\mathrm{Fetch}

(\mathrm{PC}+4)

…

A 32-bit multi-cycle RISC processor has

\mathrm{CPI}_R=4

,

\mathrm{CPI}_{lw}=5

,

\mathrm{CPI}_{sw}=4

…

Derive the average CPI of a multi-cycle RISC processor as a function of the five non-negative mix fractions

f_R

…

The following 4-bit FSM state encodings are used by a multi-cycle RISC controller:

S_\mathrm{Fetch}=0001

…

An R-type instruction with encoding

0\text{x}00\mathrm{A}43022

(opcode 000000, rs=5, rt=4, rd=6, shamt =00000…

Let

C_i

be the cycle count of instruction i on a multi-cycle RISC processor, where

C_i\in\{3,4,5\}

as determined…