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ProblemCourse & topicStatus
Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Verification SafetyEmbedded Systems Problem Solving
State-machine verification and safety boundariesEmbedded Systems · Mixed review
—Showing 24 of 50 matching problems.
A descending full-descending process stack occupies the half-open range [0x20007C00,0x20008000). The MPU is enabled with PRIVDEFENA=1 and ENABLE=1. A DMA controller is an AHB bus-matrix master and does not consult the CPU MPU.
MPU region 4 has base B=0x20030000 and SIZE=11 (size 4kiB, s=12). Three MPU regions are enabled, with higher region number winning on overlap…
Memory-type attributes of an MPU region are packed as a triple (TEX[2:0],C,B) together with a shareable… A write-back write-allocate D-cache has 32-byte lines.
A Cortex-M7-style core runs at fCPU=160.0MHz. A write-back D-cache with 32-byte lines holds one valid dirty line L for addresses…
A Harvard tightly-coupled memory provides an ITCM port and a DTCM port that may complete in the same core cycle.
A D-cache is 2-way set-associative with 4 sets and 16-byte lines, write-back, write-allocate, LRU.
Flash is accessed over AHB at fHCLK=180.0MHz with a wait-state machine: a non-sequential… A 4-way set-associative D-cache of 16kiB with 32-byte lines supports way lockdown. A three-master, four-slave AHB bus matrix has masters MI (CPU instruction), MD (CPU data), and MDMA… SRAM1 is a single-port slave on the matrix of Problem 264.
An AHB-to-APB bridge connects fHCLK=120.0MHz to fPCLK=30.00MHz… A fixed-priority AHB arbiter at SRAM1 uses DMA priority 0 (highest) and CPU data priority 1.
The AHB default slave responds to every unmapped address with a two-cycle error: in the cycle of the request the…
Flash wait states depend on HTRANS.
Two DMA channels and the CPU data port contend for a single-port APB bridge SP. A fully preemptive uniprocessor Anvil-M4 runs ForgeOS.
ForgeOS provides a 16-bit event group E stored little-endian at SRAM address 0x20001800, initially… A ForgeOS message queue Q occupies SRAM at 0x20002000 and holds at most N=4 messages. ForgeOS mutexes exist in two varieties.