Digital Logic · Finite-state-machine design
A 4-bit synchronous binary up-counter is built from four falling-edge-triggered JK…
Problem
A 4-bit synchronous binary up-counter is built from four falling-edge-triggered JK flip-flops \(Q_3Q_2Q_1Q_0\), with \(Q_3\) the most significant bit. The circuit realises a standard binary count: each stage has \(J_i=K_i\) equal to the logical AND of all less-significant \(Q\) outputs (and \(J_0=K_0=1\)). No external count-enable is present. The common clock is a \(8.00\,\mathrm{MHz}\) square wave. The present state is \(Q_3Q_2Q_1Q_0=1011\). (a) Write \(J_i\) and \(K_i\) for \(i=0,1,2,3\) as Boolean functions of the \(Q\) outputs. (b) Determine the next state after one falling clock edge. (c) Determine the frequency of each of \(Q_0\), \(Q_1\), \(Q_2\), and \(Q_3\). (d) Determine the number of clock cycles after which the counter first returns to \(1011\), starting from the present state.
Hint
A JK pair tied together is a T flip-flop: bit \(i\) toggles iff the AND of all less-significant \(Q\) bits is \(1\).
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