Digital Logic · Arithmetic units and datapath composition
A processor is byte-addressable, has a 20-bit byte address A_(19)… A_0, and has a…
Problem
A processor is byte-addressable, has a \(20\)-bit byte address \(A_{19}\ldots A_0\), and has a \(32\)-bit data bus. It performs only aligned \(32\)-bit word transfers. Main memory consists of \(256\mathrm{K}\) words of \(32\) bits. (a) Show that the memory contains exactly \(2^{20}\) bytes, and therefore that the \(20\)-bit byte address is necessary and sufficient. (b) For byte address \(\mathrm{3C00A}_{16}\), give the \(18\)-bit word index \(A_{19}\ldots A_2\) as a hexadecimal value and the \(2\)-bit byte offset \(A_1A_0\). (c) State whether \(\mathrm{3C00A}_{16}\) is an aligned word address. Give the nearest aligned word addresses immediately below and immediately above it. (d) If the memory is built from \(64\mathrm{K}\times 8\) SRAM chips, determine the number of chips required.
Hint
A \(32\)-bit word occupies four byte addresses; the word index is the byte address with the two low bits removed.
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