A matched NMOS pair with ideal tail I_(SS)=0.500 mA and drain resistors…

A matched NMOS pair with ideal tail \(I_{SS}=0.500\,\mathrm{mA}\) and drain resistors \(R_{D1}=R_{D2}=R_D=4.00\,\mathrm{k}\Omega\) to \(V_{DD}\) is used as a fully differential amplifier. Device \(g_m=4.00\,\mathrm{mS}\) at the balanced point, \(\lambda=0\). A small-signal disturbance \(v_{dd}\) appears on the \(V_{DD}\) rail (positive-supply ripple) while the input gates are AC-grounded in the differential sense (\(v_{id}=0\)) and held at a fixed common-mode voltage with infinite bypass to the signal ground used for \(v_{od}\). (a) If \(R_{D1}=R_{D2}\) exactly, determine \(v_{od}/v_{dd}\). Explain using symmetry. (b) Now \(R_{D1}=4.00\,\mathrm{k}\Omega\) and \(R_{D2}=4.08\,\mathrm{k}\Omega\) (a +2.00% mismatch on \(R_{D2}\) only). With the tail still ideal and the sources of \(M_1,M_2\) joined, determine the small-signal \(v_{od}/v_{dd}\). Treat the pair as two CS devices whose sources are not AC ground: first compute the common source-node voltage, or equivalently use superposition with matched \(g_m\) and the first-order mismatch. Report the numerical PSRR of the differential output, \(\lvert v_{dd}/v_{od}\rvert\), as a ratio and in decibels. (c) The same 2.00% drain-resistor mismatch is now assessed for a purely common-mode gate input \(v_{icm}\) with a tail resistance \(R_{SS}=40.0\,\mathrm{k}\Omega\) and a clean \(V_{DD}\). Using \[ A_{cm,\mathrm{diff}}\approx A_{cm,\mathrm{se}}\frac{\Delta R_D}{R_D},\qquad A_{cm,\mathrm{se}}\approx\frac{-R_D}{2R_{SS}} \] (or an exact half-circuit equivalent you derive), evaluate \(v_{od}/v_{icm}\) and compare its magnitude with \(\lvert v_{od}/v_{dd}\rvert\) of part (b). Interpret which disturbance is more dangerous for this particular mismatch.

With \(\lambda=0\) a MOSFET drain current does not care about the drain voltage; unmatched \(R_D\) cannot create a current mismatch by itself.