Computer Architecture · Datapath and control implementation
IEEE-754 binary32 operations are performed with round-to-nearest, ties-to-even, and…
Problem
IEEE-754 binary32 operations are performed with round-to-nearest, ties-to-even, and with traps disabled. For each operation below, list every flag among \(\{\text{invalid},\text{ overflow},\text{ underflow},\text{ divide-by-zero},\text{ inexact}\}\) that the default exception handling must raise, and give the default result as a \(32\)-bit encoding. Use the after-rounding definition of underflow: underflow is raised if and only if the computed result is tiny (subnormal or zero) and inexact. Use the canonical quiet NaN \(0\ 11111111\ 10000000000000000000000\) when a quiet NaN is the default result. (a) \((+\infty)+(-\infty)\), where \(+\infty\) is \(0\ 11111111\ 00000000000000000000000\) and \(-\infty\) is \(1\ 11111111\ 00000000000000000000000\). (b) \(M+M\), where \(M\) is the largest finite binary32 value \(0\ 11111110\ 11111111111111111111111\). (c) \(P\times Q\), where \(P\) is the smallest positive normal \(0\ 00000001\ 00000000000000000000000\) and \(Q\) is \(2^{-24}\) encoded as \(0\ 01100111\ 00000000000000000000000\). (d) \(1.0\div(+0)\), where \(1.0\) is \(0\ 01111111\ 00000000000000000000000\) and \(+0\) is \(0\ 00000000\ 00000000000000000000000\). (e) \((+0)\div(+0)\), with \(+0\) as in (d).
Hint
Match each case to a standard default-exception rule: invalid \(\infty-\infty\) or \(0/0\); overflow of a huge finite; underflow of a tiny inexact; divide-by-zero of a nonzero finite by zero.
Check your work
Work the problem yourself first. Then open it in Training to check your answer and read the full worked solution.
The answer check and full solution for this problem come with ProofAnvil Practice membership ($19 USD monthly). See membership. Or start with the free Computer Architecture sample problem: Try the free sample problem.
More Computer Architecture practice problems
- A processor uses 32-bit little-endian memory and 32-bit instructions that are always…Instruction-set architecture and assembly semantics
- Encode each of the decimal integers -73, -1, 0, 1, and 119 as an 8-bit two's-complement…Instruction-set architecture and assembly semantics
- A J-type jump instruction has the 32-bit encoding `0x0810000F`Datapath and control implementation
- A 32-bit multi-cycle RISC processor executes the six-instruction sequence below…Pipelining, hazards, and speculation
- Register file contents before execution, all values 32-bit two's complement: x1 =…Pipelining, hazards, and speculation
- A 5-stage in-order pipeline (IF, ID, EX, MEM, WB) issues at most one instruction per…Caches, virtual memory, and memory hierarchy
- A MIPS-style delayed branch has a 1-instruction delay slot that is always executed…Caches, virtual memory, and memory hierarchy
- A shared bus has three masters M_0,M_1,M_2 and a nonpreemptive round-robin arbiterI/O, interrupts, and concurrency
- Roofline time is the max of a compute ceiling and a bandwidth ceilingParallel architecture and performance limits