Computer Architecture · Caches, virtual memory, and memory hierarchy
A MIPS-style delayed branch has a 1-instruction delay slot that is always executed…
Problem
A MIPS-style delayed branch has a 1-instruction delay slot that is always executed, whether the branch is taken or not. Branches resolve in ID. For ``` 0x00400100 beq $s0, $s1, +2 // target = 0x0040010C if taken 0x00400104 add $t0, $t1, $t2 // delay slot 0x00400108 sub $t3, $t4, $t5 0x0040010C and $t6, $t7, $t8 ``` list the sequence of instructions that complete (reach WB) when the branch is taken, and the sequence when the branch is not taken. Assume no data stalls and that the delay-slot instruction is independent of the branch.
Hint
“Always executed” applies to the instruction at PC+4 of the branch, independent of the outcome.
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