Computer Architecture · Pipelining, hazards, and speculation
Register file contents before execution, all values 32-bit two's complement: x1 =…
Problem
Register file contents before execution, all values 32-bit two's complement: x1 = 0x00000008, x2 = 0x0000000C, x3 = 0x00000010, x4 = 0x00000004, x5 = 0x00000001, x6 = 0x00000002, x7 = 0x00000003, x8 = 0x00000000. Data memory is word-addressable on 32-bit aligned addresses and holds 0x11111111 at address 0x00000010 and 0x22222222 at address 0x00000014; all other words are 0x00000000. The pipeline is the classic 5-stage RISC pipeline. Instructions, in fetch order, with encodings: (I1) ADD x9, x1, x2 with machine word 0x002084B3; (I2) LW x10, 0(x3) with machine word 0x0001A503; (I3) ADD x11, x5, x6 with machine word 0x006282B3; (I4) SW x7, 4(x4) with machine word 0x00722223. Assume no stalls. At the end of cycle 5 (after the rising edge that captures the fifth cycle's combinational results into the pipeline registers), state the 32-bit value stored in EX/MEM.ALUResult and the 32-bit value stored in MEM/WB.ReadData. ADD is R-type opcode 0110011, funct3 000, funct7 0000000. LW is I-type opcode 0000011, funct3 010. SW is S-type opcode 0100011, funct3 010. The ALU in EX adds rs1 data to rs2 data for ADD and adds rs1 data to the sign-extended immediate for LW and SW.
Hint
After five stall-free cycles the oldest instruction is finishing WB and the third instruction is finishing EX.
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