A 32-bit multi-cycle RISC processor executes the six-instruction sequence below…

A 32-bit multi-cycle RISC processor executes the six-instruction sequence below, starting with \(\mathrm{PC}=0\text{x}00400000\). Instruction encodings follow opcode \([31:26]\), \(rs\) \([25:21]\), \(rt\) \([20:16]\), \(rd\) \([15:11]\), shamt \([10:6]\), funct \([5:0]\) for R-type, and opcode/\(rs\)/\(rt\)/imm for I-type. Cycle counts are: R-type 4, lw 5, sw 4, beq 3, addi 4. The sequence, given as 32-bit hex words at successive word addresses, is: - \(0\text{x}00400000\): \(0\text{x}20080005\) \(\quad(\mathrm{addi}\;\$8,\;\$0,\;5)\) - \(0\text{x}00400004\): \(0\text{x}20090003\) \(\quad(\mathrm{addi}\;\$9,\;\$0,\;3)\) - \(0\text{x}00400008\): \(0\text{x}01095020\) \(\quad(\mathrm{add}\;\$10,\;\$8,\;\$9)\) - \(0\text{x}0040000\mathrm{C}\): \(0\text{xAC}0\mathrm{A}0000\) \(\quad(\mathrm{sw}\;\$10,\;0(\$0))\) - \(0\text{x}00400010\): \(0\text{x}8\mathrm{C}0\mathrm{B}0000\) \(\quad(\mathrm{lw}\;\$11,\;0(\$0))\) - \(0\text{x}00400014\): \(0\text{x}110\mathrm{B}0001\) \(\quad(\mathrm{beq}\;\$8,\;\$11,\;+1)\) Assume the beq is not taken. Compute (i) the number of clock cycles needed to execute the six-instruction sequence through retirement of the beq, (ii) the average CPI of the sequence, and (iii) the value of PC at the start of the first cycle of the beq. Show the per-instruction cycle contributions used in (i).

CPI of a short straight-line sequence is just (sum of per-instruction cycles) / 6. Do not insert pipeline bubbles; this is multi-cycle, not pipelined.