A 5-stage in-order pipeline (IF, ID, EX, MEM, WB) issues at most one instruction per…

A 5-stage in-order pipeline (IF, ID, EX, MEM, WB) issues at most one instruction per cycle, writes the register file in the first half of WB, and reads it in the second half of ID. No forwarding is implemented. For the MIPS-like sequence ``` I1: add $t0, $t1, $t2 I2: sub $t3, $t0, $t4 I3: and $t5, $t0, $t3 I4: or $t6, $t5, $t0 ``` classify every RAW dependence as (producer instruction, consumer instruction, destination register). For each dependence, state the earliest cycle in which the consumer may enter EX if I1 enters IF in cycle 1 and the pipeline never stalls except as required to resolve that dependence in isolation. Ignore control flow.

A RAW is a later read of a register an earlier write produces, with no intervening writer of that name. Forwarding is off, so the value is first readable from the register file.