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Embedded Systems · Timers, scheduling, and real-time constraints

Two 16-bit timers are cascaded to form a 32-bit timestamp

Problem

Two 16-bit timers are cascaded to form a 32-bit timestamp. \(\mathrm{TIM_L}\) is clocked at \(f_{\mathrm{L}}=1.000\,\mathrm{MHz}\), counts \(0,\ldots,65535\), and emits a TRGO pulse on each overflow. \(\mathrm{TIM_H}\) is clocked by that TRGO, so it increments once per \(65536\,\mu\mathrm{s}\). Software reads a 32-bit time by the protocol: read \(H_1=\mathrm{CNT}_H\), read \(L=\mathrm{CNT}_L\), read \(H_2=\mathrm{CNT}_H\). If \(H_2=H_1\), the timestamp is \((H_1\ll 16)\lor L\). If \(H_2\equiv H_1+1\pmod{2^{16}}\), an overflow of \(\mathrm{TIM_L}\) occurred during the read, and the following reconstruction is required: if \(L<32768\) the overflow preceded the read of \(L\), so use \((H_2\ll 16)\lor L\); if \(L\ge 32768\) the overflow followed the read of \(L\), so use \((H_1\ll 16)\lor L\). Pin \(\mathrm{PA0}\) is unused. Ignore TRGO insertion delay. (a) Compute the increment period of \(\mathrm{TIM_H}\) and the wrap period of the 32-bit pair, in seconds. (b) A coherent read returns \(H_1=\mathtt{0x00A1}\), \(L=\mathtt{0xFFF0}\), \(H_2=\mathtt{0x00A1}\). Compute the 32-bit tick count and the time in seconds. (c) A torn read returns \(H_1=\mathtt{0x00A1}\), \(L=\mathtt{0x0002}\), \(H_2=\mathtt{0x00A2}\). Reconstruct the timestamp. Then compute the incorrect timestamps obtained by blindly using \((H_1\ll 16)\lor L\) and by blindly using \((H_2\ll 16)\lor L\), and report each error in ticks. (d) Another torn read returns \(H_1=\mathtt{0x00A1}\), \(L=\mathtt{0xFFF8}\), \(H_2=\mathtt{0x00A2}\). Reconstruct the timestamp using the stated rule. Explain in one sentence why \(L\ge 32768\) selects \(H_1\) rather than \(H_2\).

Hint

Cascaded 16-bit counters form a 32-bit tick only if the high half is sampled consistently with the low half.

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