A UART RX FIFO is 16 bytes deep

A UART RX FIFO is \(16\) bytes deep. An RXFT interrupt is asserted whenever the FIFO fill level is at least the watermark \(W=8\) bytes, and is cleared only by draining the FIFO below \(W\). An IDLE interrupt is asserted when the line has been idle for one character time after at least one byte has been received since the previous idle, and is cleared by reading the UART status and data path as specified below. Character format is 8N1 at \(2.000\,\mathrm{Mbit/s}\) (bit rate \(2.000\,\mathrm{MHz}\)). A burst of \(45\) bytes arrives back-to-back with no idle between them, after which the line is idle for many character times. Each RXFT ISR reads exactly \(8\) bytes from the FIFO (or until empty, whichever first). The IDLE ISR reads every remaining byte until the FIFO is empty. ISR CPU time is \(1.50\,\mu\mathrm{s}\) plus \(0.40\,\mu\mathrm{s}\) per byte read. No overflow occurs unless a part explicitly asks about fill level. (a) Compute the character time in microseconds. Compute the wall-clock duration of the \(45\)-byte burst. (b) Determine the number of RXFT ISR entries and the number of IDLE ISR entries caused by this burst-then-idle pattern. Compute the total number of bytes read in RXFT ISRs and in the IDLE ISR. (c) Compute the total ISR CPU time and the CPU occupancy over the burst interval of (a) (do not include idle time after the burst in the occupancy denominator). (d) Suppose instead that each RXFT ISR is delayed so that it begins only \(40.0\,\mu\mathrm{s}\) after the watermark is first reached, during which the burst continues at full rate. Starting from an empty FIFO, determine the peak FIFO fill level at the first RXFT ISR entry, and decide whether a \(16\)-byte FIFO overflows before that first drain. Repeat for a delay of \(50.0\,\mu\mathrm{s}\).

Watermark interrupts drain in chunks of \(W\); IDLE is what harvests the leftover after the line goes quiet.