A complementary PWM pair drives one leg of an H-bridge

A complementary PWM pair drives one leg of an H-bridge. Timer \(\mathrm{TIM1}\) is edge-aligned with \(f_{\mathrm{cnt}}=72.00\,\mathrm{MHz}\), \(\mathrm{ARR}=3599\), and PWM mode 1 on channel 1: pin \(\mathrm{PE8}=\mathrm{TIM1\_CH1}\) (high-side command before dead time) is high iff \(0\le\mathrm{CNT}<\mathrm{CCR1}\). Pin \(\mathrm{PE9}=\mathrm{TIM1\_CH1N}\) (low-side command before dead time) is the logical complement of \(\mathrm{PE8}\). A dead-time generator delays each transistor's turn-on by \[ t_{\mathrm{dt}}=N_{\mathrm{dt}}/f_{\mathrm{dt}},\qquad f_{\mathrm{dt}}=72.00\,\mathrm{MHz},\qquad N_{\mathrm{dt}}=72, \] and does not delay turn-off. Consequently both transistors are off for \(t_{\mathrm{dt}}\) after every commanded transition, and each device's on-time is \(t_{\mathrm{dt}}\) shorter than the corresponding complementary command. \(\mathrm{CCR1}=1440\). Ignore switching delay of the FETs beyond the inserted dead time, and ignore bootstrap constraints. (a) Compute the PWM period, the PWM frequency, \(t_{\mathrm{dt}}\), the ideal high-side on-time (before dead time), and the ideal low-side on-time. (b) Compute the actual high-side on-time and actual low-side on-time after dead-time insertion, and the total time per period during which both devices are off. (c) Define the effective high-side duty as actual high-side on-time divided by the PWM period. Compute that duty, and compute the relative reduction from the commanded duty \(\mathrm{CCR1}/(\mathrm{ARR}+1)\). (d) Determine the smallest integer \(\mathrm{CCR1}\) for which the actual high-side on-time is still strictly positive, and the largest integer \(\mathrm{CCR1}\le\mathrm{ARR}+1\) for which the actual low-side on-time is still strictly positive. Translate both bounds into commanded duty.

Dead time eats a fixed interval from every turn-on and from both devices at each commanded edge.