GPIOA on Anvil-M0 provides three 32-bit registers that affect the same 16 output…

GPIOA on Anvil-M0 provides three 32-bit registers that affect the same 16 output latches \(\mathrm{ODR}[15:0]\). Unused upper bits of each register read as zero and ignore writes. Starting value: \(\mathrm{ODR}=\mathtt{0x0000C351}\). The port pins are all outputs. - A write of word \(X\) to \(\mathrm{ODR}\) replaces \(\mathrm{ODR}[15:0]\) by \(X[15:0]\). - A write of word \(S\) to \(\mathrm{SET}\) sets every latch \(n\) for which \(S[n]=1\) and leaves latches with \(S[n]=0\) unchanged. - A write of word \(C\) to \(\mathrm{CLR}\) clears every latch \(n\) for which \(C[n]=1\) and leaves latches with \(C[n]=0\) unchanged. The desired update is: set pin \(2\), clear pin \(8\), and leave every other latch unchanged. No concurrent writer exists. Ignore pull-ups, modes, and BSRR. (a) Decode \(\mathtt{0xC351}\) into bits \(15\) through \(0\). State the present values of pins \(2\) and \(8\). (b) Compute the 16-bit image that a read-modify-write to \(\mathrm{ODR}\) must write, namely \((\mathrm{ODR}\mathbin{|}\mathtt{0x0004})\mathbin{\&}\mathord\sim\mathtt{0x0100}\), and give it as four hexadecimal digits. (c) Compute a \(\mathrm{SET}\) write word and a \(\mathrm{CLR}\) write word that together realize the same update (order: SET then CLR). Give each as eight hexadecimal digits, with bits \(31:16\) equal to \(0\). (d) Starting from \(\mathtt{0xC351}\), determine the \(\mathrm{ODR}\) that results if the firmware writes \(\mathtt{0x0004}\) to \(\mathrm{ODR}\) instead of to \(\mathrm{SET}\), intending to “set pin \(2\).” Identify every latch that is corrupted relative to the requirement. Then state, using only the three register semantics, why a SET write of \(\mathtt{0x0004}\) does not have that corruption.

Writing ODR replaces every latch; writing SET or CLR names only the one-bits.