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Embedded Systems · Interrupts, concurrency, and shared state

USART2 is clocked by f_CK=36.00 MHz

Problem

USART2 is clocked by \(f_{\mathrm{CK}}=36.00\,\mathrm{MHz}\). For \(\mathtt{OVER8}=0\), the 16-bit BRR packs a 12-bit mantissa \(m\) in bits \([15:4]\) and a 4-bit fraction \(f\) in bits \([3:0]\), with \[ \mathtt{USARTDIV}=m+f/16,\qquad f_{\mathrm{baud}}=f_{\mathrm{CK}}/(16\cdot\mathtt{USARTDIV}). \] For \(\mathtt{OVER8}=1\), BRR packs \(m\) in bits \([15:4]\) and a 3-bit fraction \(f_8\) in bits \([2:0]\) (bit \(3\) must be \(0\)), with \[ \mathtt{USARTDIV}=m+f_8/8,\qquad f_{\mathrm{baud}}=f_{\mathrm{CK}}/(8\cdot\mathtt{USARTDIV}). \] The target baud rate is \(115200\,\mathrm{Bd}\). \(m\) is a positive integer and the fraction field is an integer in its legal range. (a) With \(\mathtt{OVER8}=0\), compute the exact real \(\mathtt{USARTDIV}\) that would produce \(115200\,\mathrm{Bd}\) with no error. Then quantise to the nearest multiple of \(1/16\) (halfway away from zero toward \(+\infty\)), encode BRR as a 16-bit hexadecimal value, and compute the actual baud and the signed relative error \((f_{\mathrm{baud}}-115200)/115200\). (b) Repeat part (a) with \(\mathtt{OVER8}=1\), quantising to the nearest multiple of \(1/8\). (c) Determine which oversampling setting yields the smaller absolute relative error, and compute the bit-time error accumulated over one 10-bit frame (start + 8 data + stop) at the actual baud of that setting, in microseconds, relative to the ideal \(115200\,\mathrm{Bd}\) frame duration. (d) If BRR is programmed as \(\mathtt{0x0027}\) with \(\mathtt{OVER8}=0\), decode \(m\) and \(f\), compute \(f_{\mathrm{baud}}\), and state whether this encoding matches part (a).

Hint

The exact divisor is \(f_{\mathrm{CK}}\) divided by \(16\) (or \(8\)) times the target baud; it generally does not already lie on the hardware grid.

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